The present invention relates to a sense amplifier circuit which is used in an electrically programmable nonvolatile semiconductor memory or the like and, more particularly, to a sense amplifier circuit for comparing a bit line potential on the memory cell side and a reference potential on the dummy cell side.
An electrically programmable nonvolatile memory, for example, an electrically programmable read only memory (EPROM) of the ultraviolet erasing type, is constituted so as to have a memory cell array 1 and a sense amplifier 3, as shown in FIG. 1. In memory cell array 1, memory cells MC of, e.g., the floating gate type, are arranged in a matrix form, and word lines WL.sub.1 to WL.sub.M and bit lines BL.sub.1 to BL.sub.N are selectively coupled to those memory cells. One end of each of N-channel MOS transistors QB.sub.1 to QB.sub.N for selecting the bit lines is commonly connected to a node NB. Bit lines BL.sub.1 to BL.sub.N are respectively connected to the other ends of MOS transistors QB.sub.1 to QB.sub.N. MOS transistors QB.sub.1 to QB.sub.N are connected such that their conduction states are controlled by an output of a column decoder (not shown). Node NB is connected to an input terminal of a bit line potential amplifier circuit 2 whose output terminal is connected to an input node N.sub.1 of a differential amplifier type comparator 3 such as a P-channel current mirror type comparator. Amplifier circuit 2 includes an enhancement type N-channel MOS transistor Q.sub.1 connected between bit line node NB and a power source terminal VC; an enhancement type N-channel MOS transistor Q.sub.2 whose one end is connected to bit line node NB; and an enhancement type P-channel MOS transistor Q.sub.3 whose gate and drain are connected to the other end of MOS transistor Q.sub.2 and whose source is connected to power source terminal VC. A predetermined bias voltage VBA is applied from a bias voltage generator 4 to the gates of MOS transistors Q.sub.1 and Q.sub.2 through a bias line BSL. Bias voltage generator 4 comprises: a P-channel MOS transistor Q.sub.4 which is connected between power source terminal VC and bias line BSL and whose gate is grounded; an N-channel MOS transistor Q.sub.5 whose gate and drain are connected to bias line BSL; and an N-channel MOS transistor Q.sub.6 whose gate and drain are connected to the source of MOS transistor Q.sub.5 and whose source is grounded.
Each of memory cells MC in memory cell array 1 is selectively set either to the state in which data was written, i.e., the state ("0" state) in which a threshold voltage V.sub.TH is high, or the erasing state in which no data is written, i.e., the state ("1" state) in which threshold voltage V.sub.TH is low. Therefore, in the reading mode, the data read out of the selected memory cell is amplified to bit line potential VB by bit line potential amplifier circuit 2 and, thereafter, it is supplied to one input terminal N.sub.1 of comparator 3. In this case, it is assumed that when the data read out of the memory cell in the "0" or "1" state is amplified by amplifier circuit 2, it is converted into bit line potential VB.sub.0 and VB.sub.1, respectively.
A MOS transistor Q.sub.7 for controlling the writing operation whose conduction state is controlled in accordance with inverted data D.sub.in of write data D.sub.in is connected between bit line node NB and a high voltage terminal VP to which a writing voltage is applied. Therefore, it is possible, when writing data into the selected memory cell, to apply a high voltage VP to the drain of the selected memory cell in which a high voltage is also applied to the control gate.
Comparator 3 is the current mirror circuit comprising two N-channel MOS transistors Q.sub.8 and Q.sub.9 for amplification and two P-channel MOS transistors Q.sub.10 and Q.sub.11 serving as loads.
A reference voltage generator 5 is used to apply a reference voltage V.sub.ref to the other input terminal N.sub.2 of comparator 3 and has a bit line potential amplifier circuit 6 which is constituted in a manner almost similar to bit line potential amplifier circuit 2. Amplifier circuit 6 includes: MOS transistors Q.sub.1A through Q.sub.3A which are constituted and connected in a manner similar to MOS transistors Q.sub.1 through Q.sub.3 in amplifier circuit 2; and a MOS transistor Q.sub.12 connected between power source terminal VC and input terminal N.sub.2. Reference potential generator 5 further has a floating gate type dummy cell DC in which one end is grounded and the other end is connected to amplifier circuit 6 through a bit line BLD and an N-channel MOS transistor QBD. Dummy cell DC is set into the erasing state ("1" state) and power source voltage VC is applied to the control gates of dummy cell DC and MOS transistor QBD.
Reference potential V.sub.ref, which is generated from reference potential generator 5, must be set to satisfy the relation of VB.sub.0 &gt;V.sub.ref &gt;VB.sub.1, i.e., so that V.sub.ref is lower than potential VB.sub.0 at which the bit line is set when the data is read out of the memory cell in the "0" state and so that V.sub.ref is higher than potential VB.sub.1 at which the bit line is set when the data is read out of the memory cell in the "1" state. For this reason, comparator 3 can certainly generate the output signal corresponding to the data read out of the selected memory cell. Thus, conventionally, MOS transistor Q.sub.12 is connected in parallel with MOS transistor Q.sub.3A, which is the same size as MOS transistor Q.sub.3, as the resistance load of the bit line in reference potential generator 5. Consequently, the synthesized ON reference of MOS transistors Q.sub.3A and Q.sub.12 is smaller than the ON resistance of MOS transistor Q.sub.3 and the relation of V.sub.ref &gt;VB.sub.1 is derived. In this manner, reference potential V.sub.ref is set to a value between potentials VB.sub.0 and VB.sub.1 for a standard power source voltage VCS of, e.g., 5 V.
As shown in FIG. 2, reference potential V.sub.ref and bit line potentials VB.sub.0 and VB.sub.1 vary in accordance with a change in power source voltage VC. As will be obvious from FIG. 2, reference potential V.sub.ref changes at an increase rate larger than that of bit line potential VB.sub.0 in association with an increase in power source voltage VC. When power source voltage VC rises to a VC.sub.1 level of, e.g., 6 V, reference potential V.sub.ref becomes almost equal to bit line potential VB.sub.0. When power source voltage VC further increases, V.sub.ref becomes larger than VB.sub.0, causing a malfunction of the sense amplifier circuit.
The difference of dependency on power source voltage VC between bit line potential VB.sub.0 and reference potential V.sub.ref is caused by the difference between the size of load MOS transistor Q.sub.3 in amplifier circuit 2 and the total size of load MOS transistors Q.sub.3A and Q.sub.12 in reference potential generator 5.
In the sense amplifier circuit shown in FIG. 1, the allowable range between a standard power source voltage VCS and the maximum allowable power source voltage VC.sub.1, namely, the power source voltage margin, cannot be set to a sufficiently large value. Therefore, not only is a malfunction of comparator 3 likely to occur due to a variation in power source voltage VC, but there is also a possibility of causing a malfunction of comparator 3 by other factors, for example, by variations in circuit element parameters and in writing voltage into the memory cell as well. For example, even if reference potential generator 5 is designed to generate proper reference potential V.sub.ref when it is driven by standard power source voltage VCS (=5 V), there is a case where the sense amplifier circuit in the memory IC actually manufactured cannot normally operate at a power source voltage VC =5 V because of a variation in element parameters due to a fluctuation in manufacturing processes.